The present invention relates generally to testing memory devices, and, more particularly, to methods for generating worse-than-normal memory test conditions.
Every memory chip goes through a series of functional tests before being packaged and shipped to a customer. If a faulty chip is assembled on a system board, debugging and dissembling it will be very costly. So screening out all faulty chips before they are shipped is a very important step in manufacturing the memory chips. Besides, as memory chips may operate in worse-than-normal and very noisy field environments, their test conditions should also emulate the field environments to screen out weaker chips.
Conventional DRAM tests comprise a series of write-and-read operations to have every bit of the memory chip being accessed. For example, a March pattern can be shown as following:(w0)↑(r0, w1)↑(r1, w0)↓(r0)where w0 means ‘write 0’, r0 means ‘read 0’, and similarly, w1 means ‘write 1’, r1 means ‘read 1’. Symbol ‘↑’ means incrementing addresses, and symbol ‘↓’ means decrementing addresses, referring to Schanstra and A. J. Van De Goor, “Industrial Evaluation of DRAM Tests”, Proc. Design, Automation and Test in Europe, 1999, pp. 623-630.
The read-and-write operations inside a pair of parentheses are applied to one byte or one word of cells and the operations step through the whole memory. Here a byte has 8 bits of cells, and a word has 16 bits of cells. Some memory chips may have bandwidths other than 8 or 16 bits. Then ‘(r0, w1)↑’ means first reading a byte or a word, which is supposed to be a ‘0’, if not, then there must be at least one faulty bit in that byte or word, then writing ‘1’ into it.
There are other test patterns with different combinations of write-and-read that can generate different kinds of disturbances to detect fault bits in a DRAM chip. But often these tests operate at just normal disturbance conditions. A worse than normal test condition may require the presence of individual or in combination of following conditions: (1) lowered supply voltage and high temperature, (2) cell data being weakened, the stored charge decayed, (3) stress from accessing neighboring cells at worst. For examples, if a cell stored decayed charges but surrounded by neighboring cells with newly written opposite charge polarity, reading this cell may have high probability noise coupling. Most test patterns do not create this environment and stress, but this condition is valid and can happen in practical memory products.
One of conventional ways of lowering supply voltage (Vdd) to weaken a cell is to directly toggle the Vdd. But Vdd has heavy capacitance load, and switching it normally takes milliseconds in production testers, which makes switching Vdd during every write-and-read cycle impractical.
A DRAM cell weakening method is to insert delay time so that charges stored in DRAM cells are extra decayed, and hence weakened. But this method also increases test time, and are not practical.
What is needed is a test method to align maximum number of worse-than-normal test conditions without increasing test time.